Now there’s a direct link between DSP and FPGA design environments. AccelChip’s unique high-level synthesis tool reads MATLAB and Simulink designs and outputs synthesizable RTL models and testbenches compatible with all FPGA design flows. AccelFPGA automatically creates synthesizable RTL models and simulation testbenches eliminating months of engineering time. The automated path from MATLAB and Simulink to RTL design flows eliminates ambiguous specifications and costly design spins. The architecture-aware compiler produces optimized RTL models for the targeted FPGA device.