Calypto Design Systems leads the industry in technologies for ESL hardware design and RTL power optimization. These technologies empower designers to create high quality and low power electronic systems for today’s most innovative electronic products. Calypto's best-in-class technologies focus on high-level synthesis, RTL power optimization and functional verification. Catapult lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production quality RTL to dramatically shorten both design and verification in today’s hardware design flows. PowerPro is an automated RTL power optimization and analysis product that identifies and inserts sequential clock gating and memory enable logic into synthesizable Verilog and VHDL designs. PowerPro has proven to reduce power by up to 60% in RTL designs. SLEC is a sequential equivalence checker that handles differences in design state, timing and levels of abstraction. SLEC enables ESL hardware design by using formal methods to comprehensively proving equivalence between RTL implementations and system-level models.